Publications of Amity University, Gurugram

Amity Education Valley Gurugram, Manesar, Panchgaon, Gurgaon, Haryana, India

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Performance and a new 2-D analytical modeling of a dual-halo dual-dielectric triple-material surrounding-gate-all-around (DH-DD-TM-SGAA) MOSFET

An Accurate 2D Analytical Model for Transconductance to Drain Current ratio (gm/Id) for a Dual Halo Dual Dielectric Triple Material Cylindrical Gate All Around MOSFETs

MODELING AND ANALYSIS OF THRESHOLD VOLTAGE FOR DUAL-HALO DUAL-DIELECTRIC TRIPLE-MATERIAL SURROUNDING-GATE METAL–OXIDE–SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

Implementation of Various Error Detection and Correction Techniques in Communication

Wireless Data Transmission using Hand Gesture

Comparison of Hand Gesture Techniques for Telemetry system

DESIGN CHARGE-PUMP PHASE-LOCKED LOOP (CPPLL) USING 0.35µm VLSI TECHNOLOGY

FUTURISTIC SMART RIDING HELMET

CMOS DESIGN OF Ka-BAND POWER AMPLIFIER FOR SATELLITE APPLICATIONS

A technical review on low power VLSI arithmetic circuits

Amity University, Gurugram

Performance and a new 2-D analytical modeling of a dual-halo dual-dielectric triple-material surrounding-gate-all-around (DH-DD-TM-SGAA) MOSFET

An Accurate 2D Analytical Model for Transconductance to Drain Current ratio (gm/Id) for a Dual Halo Dual Dielectric Triple Material Cylindrical Gate All Around MOSFETs

MODELING AND ANALYSIS OF THRESHOLD VOLTAGE FOR DUAL-HALO DUAL-DIELECTRIC TRIPLE-MATERIAL SURROUNDING-GATE METAL–OXIDE–SEMICONDUCTOR FIELD-EFFECT TRANSISTORS

Implementation of Various Error Detection and Correction Techniques in Communication

Wireless Data Transmission using Hand Gesture

Comparison of Hand Gesture Techniques for Telemetry system

DESIGN CHARGE-PUMP PHASE-LOCKED LOOP (CPPLL) USING 0.35µm VLSI TECHNOLOGY

FUTURISTIC SMART RIDING HELMET

CMOS DESIGN OF Ka-BAND POWER AMPLIFIER FOR SATELLITE APPLICATIONS

A technical review on low power VLSI arithmetic circuits

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