Ms Ashvini Byri

Ashvini B. is a seasoned SoC Performance Modeling Engineer with over 10 years of experience in hardware engineering, currently working at AMD in San Jose, California. She specializes in architecture performance modeling, focusing on identifying bottlenecks and enhancing system performance. Her expertise includes leading the integration of NAND memory components, conducting comprehensive system simulations, and implementing advanced features to improve capabilities and reliability. Previously, Ashvini served as a Staff Engineer at Western Digital, where she spearheaded NAND memory bring-up processes, collaborated with cross-functional teams to optimize performance, and conducted end-to-end traffic simulations across various architecture platforms. Her proficiency in leveraging performance measurement tools, particularly Delphi, has enabled her to perform detailed analyses of system performance metrics. Ashvini's technical skill set includes multiple programming languages such as Python, C++, and Verilog, as well as experience with tools like Trace32, Eclipse, and Cadence Virtuoso. She has a proven track record in post-silicon DDR bring-up tests and memory validation, consistently delivering high-quality results in SoC design. A continuous learner, Ashvini is committed to expanding her expertise in post-silicon validation and is eager to connect with fellow professionals in hardware engineering and technological innovation. With a strong focus on delivering impactful results, she remains a valuable asset in the field of semiconductor design and performance analysis.

• Python
• CPU design
• System on a Chip (SoC)
• Cadence ADE-L
• Xilinx ISE
• C
• Matlab
• Keil
• VHDL
• C++
• FPGA
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