Ashvini Byri

Ashvini B. is a seasoned SoC Performance Modeling Engineer with over 10 years of experience in hardware engineering, currently working at AMD in San Jose, California. She specializes in architecture performance modeling, focusing on identifying bottlenecks and enhancing system performance. Her expertise includes leading the integration of NAND memory components, conducting comprehensive system simulations, and implementing advanced features to improve capabilities and reliability. Previously, Ashvini served as a Staff Engineer at Western Digital, where she spearheaded NAND memory bring-up processes, collaborated with cross-functional teams to optimize performance, and conducted end-to-end traffic simulations across various architecture platforms. Her proficiency in leveraging performance measurement tools, particularly Delphi, has enabled her to perform detailed analyses of system performance metrics. Ashvini's technical skill set includes multiple programming languages such as Python, C++, and Verilog, as well as experience with tools like Trace32, Eclipse, and Cadence Virtuoso. She has a proven track record in post-silicon DDR bring-up tests and memory validation, consistently delivering high-quality results in SoC design. A continuous learner, Ashvini is committed to expanding her expertise in post-silicon validation and is eager to connect with fellow professionals in hardware engineering and technological innovation. With a strong focus on delivering impactful results, she remains a valuable asset in the field of semiconductor design and performance analysis. Ashvini Byri led a transformative initiative at SK Hynix that revolutionized system reliability through the implementation of Sudden Power Loss (SPL) protection across the company's SoC portfolio. This critical feature implementation demonstrated exceptional technical innovation and strategic foresight in addressing one of the most challenging aspects of semiconductor reliability. The project's success would establish new standards for system protection and reliability in the semiconductor industry. The project emerged from the crucial need to maintain data integrity during unexpected power interruptions, a challenge that had significant implications for both product reliability and customer confidence. Under Ashvini Byri's leadership, the initiative introduced groundbreaking approaches to power loss detection and system protection that would not only solve immediate technical challenges but also set new benchmarks for future developments. At the heart of this success story was Byri's innovative approach to testing and implementation. She pioneered the development of fake power-down tests, creating sophisticated mechanisms that could detect power loss events before they became critical. This proactive methodology represented a significant departure from traditional reactive approaches to power management. The implementation included advanced algorithms for early detection and response, ensuring that systems could initiate protective measures before critical failures occurred. Technical implementation required careful consideration of system architecture and performance requirements. Byri conceptualized and executed a strategy that enabled systems to perform essential data-saving operations and hardware protection measures during power loss events. This thoughtful approach was key to preventing costly redesigns and maintaining product development timelines. The implementation involved sophisticated power monitoring circuits, rapid response mechanisms, and intelligent data preservation protocols that could activate within microseconds of detecting potential power issues. Ashvini S. Byri is an accomplished hardware engineer with extensive experience in architecture modeling, post-silicon validation, and system-on-chip (SoC) design. With a Master’s degree in Electrical Engineering from the University of Southern California (USC) and a Bachelor’s in Electronics and Telecommunications from the University of Mumbai, Ashvini has built a robust technical foundation in advanced semiconductor technologies. Currently serving as an MTS Silicon Design Engineer at Advanced Micro Devices (AMD), she plays a critical role in data center GPU validation, automating validation processes, optimizing system deployment, and identifying data pipeline inefficiencies to enhance GPU performance. Prior to AMD, she worked at Western Digital as a Staff Engineer, leading NAND memory feature bring-up, end-to-end traffic simulations, and performance evaluations using Delphi. Her tenure at SK Hynix Memory Solutions spanned over six years, where she gained deep expertise in pre-silicon modeling, simulation, and performance analysis of SoC architectures, particularly in next-generation memory technologies like QLC NAND, Chipkill algorithms, and sudden power loss (SPL) mechanisms. She also contributed significantly to post-silicon memory validation for DDR4 DRAM, developing FPGA-based debug tools, DDR bring-up tests, SHMOO implementations, and regression testing for traffic integrity on U2 and M2 boards. Earlier in her career, she interned as a Graphical Design Engineer at Intel, contributing to pre-silicon validation within the VPG team. Her technical expertise spans a wide range of programming languages, including Python, C++, C, Java, Perl, and hardware description languages like Verilog, VHDL, and SystemVerilog. She is proficient in industry-standard tools such as Trace32, Eclipse, Cadence Virtuoso, and Xilinx ISE. Her graduate research at USC involved designing and implementing complex processor architectures, including an Out-of-Order Tomasulo processor, a multi-threaded (CMT) processor, and a 1K-bit SRAM design, among others. She successfully executed performance optimization and debugging methodologies for pre-silicon and post-silicon verification processes. Her expertise in architectural simulation, debugging, and automation has positioned her as a key contributor in advancing memory and GPU technologies. Throughout her career, she has demonstrated a strong ability to troubleshoot design deadlocks, implement regression testing, and drive architectural innovations, making her a valuable asset in the semiconductor industry.