Paper Title

LOW-LATENCY FPGA-BASED ALARM CLOCK SYSTEM ON BASYS 3 WITH REAL-TIME TIMEKEEPING AND BUZZER INTERFACE

Keywords

FPGA
Verilog
Alarm Clock
Xilinx Basys 3
Seven-Segment Display
Piezo Buzzer
Real-Time Systems
RTL Design

Article Type

Research Article

Journal

International Journal of VLSI Design

Publication Info

Volume: 2 | Issue: 1 | Pages: 1-15

Published On

April, 2025

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Abstract

This paper presents the design and implementation of a real-time digital alarm clock system on the Xilinx Basys 3 FPGA using Verilog HDL. Unlike traditional microcontroller-based designs, our FPGA-based system leverages hardware-level parallelism for enhanced timekeeping accuracy and responsiveness. The design includes time counting, alarm setting via onboard switches, and real-time display through a four-digit seven-segment display. When the current time matches the preset alarm, a piezo buzzer connected via the Pmod interface is triggered. Our implementation ensures a reliable and low-latency clock system, with features such as second-level LED indication, manual time setting, and reset functionality through push buttons. Simulation and hardware validation using Xilinx Vivado confirm the correctness of the system. Testing included accuracy checks, alarm activation, and user interaction validation. The results demonstrate high precision, low power consumption, and robust performance, making this FPGA design suitable for embedded time-sensitive applications and smart IoT integration in future work.