DATA-DRIVEN FAULT LOCALIZATION IN VLSI CHIPS USING SEMI-SUPERVISED LEARNING AND TEMPORAL TEST SIGNATURES

Abstract

The increasing complexity of Very-Large-Scale Integration (VLSI) chips presents significant challenges in fault localization, particularly as traditional deterministic testing methods struggle with scalability and coverage. This research explores the integration of semi-supervised learning techniques with temporal test signature analysis for enhanced fault detection and localization. The approach leverages both labeled and unlabeled test data to infer fault patterns by analyzing the temporal progression of test signatures. A framework is proposed that combines clustering-based semi-supervised learning and time-series analysis, enabling the identification of subtle fault behaviors across chip architectures. Evaluation on synthetic and real-world VLSI test benches demonstrates improved localization accuracy and adaptability. The study positions data-driven fault diagnosis as a vital method for post-silicon validation and yield enhancement. This methodology offers a significant contribution toward building resilient and self-diagnosing chip systems.