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Nilesh Patel

I/C Principal at M. L. Institute of Diploma Studies, Bhandu
Mehsana, Gujarat, India
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S9-082024-0905120
M. L. Institute of Diploma Studies, Bhandu
Nirma University

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26 Publications
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👤 About

Skills & Expertise

VLSI Design CMOS Technology Digital Phase Locked Loop Current Feedback Amplifier Charge Pump Circuits Phase Locked Loop Delay -Locked Loop Voltage Controlled Oscillator Phase Frequency Detector CMOS Comparator Telescopic OTA Operational Amplifier Current Conveyors Negative Current Conveyor Dual Modulus Prescaler LFSR counter Optical Lithography Multi -Gate MOSFET ASIC & FPGA Tools & Technology NPTEL Patent Search Methodology Research Methodology Nanotechnology

Research Interests

Self-motivated Teamwork Quick learner Good Presentation skills Leadership skills Energetic Positive Attitude

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💼 Experience

I/C Principal

M. L. Institute of Diploma Studies, Bhandu · January 2017 - Present
Administration & Teaching

Senior Lecturer and Head of Department of English

L.C.I.T Bhandu · October 2008 - October 2016
Teaching & Administration

Lecturer (Regular Basis)

L.C.I.T Bhandu · May 2005 - October 2008
Teaching

Lecturer (Adhoc Basis)

L.C.I.T Bhandu · July 2004 - April 2005
Teaching

Teaching Assistant (Adhoc Basis)

Swami Sachchidanand Polytechnic College (SSPC), Visnagar · December 2001 - May 2002
Teaching

🎓 Education

Nirma University

Ph. D in (VLSI Design) · 2019

Institute of Technology Nirma University Ahmadabad

M.Tech (EC) in VLSI Design · 2008

Sarvajanik College of Engineering and Technology (SCET)

B.E.(EC) in · 2000

C. U. Shah H.S School Ahmadabad

H.S.C in · 1996

Navsarjan High School, Ranip

S.S.C in · 1994
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🎤 Conferences & Seminars (13)

Multi -Gate MOSFET
Hot By · City , State , India · April, 13 -14 2012
Recent Trends in Optical Lithography
Hot By · City , State , India · April, 13 -14 2012
LFSR counter Implementation Using CMOS VLSI Technology
Hot By · City , State , India · April, 13 -14 2012
Low Power High Performance SRAM Design
Hot By · City , State , India · April, 13 -14 2012
0.35 um CMOS Current Feedback Amplifier using Negative Current Conveyor
Hot By · City , State , India · November, 27 -29 2009

Professional Memberships (4)

International Association of Engineers (IAENG)
Member: || Join dt: -
IACSIT
Member: || Join dt: -
Country: Singapore
Institution of Electronics and Telecommunication Engineers (IETE)
Member: Member || Join dt: -
Country: India
Indian Society For Technical Education(ISTE)
Member: Life Member || Join dt: -
Country: India

📚 Publications (26)

A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer CMOS Technology
Journal: International Journal of Recent Technology and Engineering • November 2019
Method for a Fast -Lock Low -Jitter Delay -Locked Loop using a Dual Charge Pump and Lock Control Circuit
Journal: International Journal of Advanced Research in Computer and Communication Engineering • November 2013
Charge Pump, Loop Filter and VCO for Phase Lock Loop Using 0.18m CMOS Technology
Journal: IOSR Journal of VLSI and Signal Processing • May. Jun. 2013
A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer CMOS Technology
Journal: International Journal of Electronics and Communication Engineering and Technology • May-June 2018
High Speed CMOS Charge Pump Circuit for PLL Applications Using 180nm CMOS Technology
Journal: International Journal of Advance Engineering and Research Development • May-2014
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