A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer CMOS Technology
Abstract
https://scholar9.com/publication-detail/a-low-jitter-low-phase-noise-wideband-digital-phas-21986
Details
Volume
8
Issue
4
Pages
3994 -3999
ISSN
2277-3878
Nilesh Patel
"A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer CMOS Technology".
International Journal of Recent Technology and Engineering,
vol: 8,
No. 4
Nov. 2019, pp: 3994 -3999,
https://scholar9.com/publication-detail/a-low-jitter-low-phase-noise-wideband-digital-phas-21986