Veera Boopathy
"The Physical Design Implementation of a 32-Bit 5-Stage Pipelined MIPS Processor using SCL 180nm Technology".
International Journal of Engineering and Advanced Technology,
vol: 9,
No. 2
Dec. 2019,
pp: ,
https://scholar9.com/publication-detail/the-physical-design-implementation-of-a-32bit-5s-24574
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