PCIe L0p low-power state verification: Pre-silicon approaches and challenges

Abstract

The PCIe 6.0 specification introduces the L0p low-power substrate, enabling dynamic link width scaling to reduce power consumption without interrupting data flow. This feature presents unique verification challenges due to its complex handshake mechanism, precise timing requirements, and backward compatibility needs. Pre-silicon verification using formal methods and simulation is essential to validate L0p logic before silicon fabrication. Formal verification confirms the correctness of state transitions, entry/exit conditions, and deadlock freedom, while simulation examines lane activation/deactivation sequences and data integrity during width changes. This article details the verification methodology for L0p, including formal proofs of the handshake process and extensive simulation of lane scaling events. Case studies highlight subtle design bugs uncovered and resolved in pre-silicon, including simultaneous width-change request deadlocks and lane reactivation sequence errors, avoiding costly post-silicon debugging. Comprehensive pre-silicon validation ensures PCIe 6.0 devices can safely leverage this power-saving mechanism while maintaining performance and interoperability.