About
Deepak Kumar Lnu is a Principal Engineer at Synopsys, Inc. with 16+ years of expertise in PCI Express (PCIe) Design and Verification, covering Gen1 through Gen7. He led the development of the industry’s first PCIe Gen7 VIP and pioneered innovations like Polling Compliance Load Board Verification. A named contributor to PCIe 6.0 and 7.0 specifications, his work enables first-silicon success for global semiconductor leaders in AI, HPC, and automotive domains. He holds multiple fellowships and is recognized globally for his technical leadership and standardization contributions.
Skills & Expertise
Core Competencies: • PCI Express (Gen1 to Gen7)
PIPE Interface
CXL
USB4
SDIO 1.0 & 2.0 • SOC & IP verification • Design & Verification of high-speed serial protocols • Client Interaction and Cross-Cultural Communication • Technical Support and Product Ownership Technical Skills: • HDL: Verilog
VHDL
System Verilog • Verification Methodologies: UVM
OVM
VMM • Programming Languages: C
C++ • Platforms: Linux
Windows • Version Control Tools: CVS
VSS
Perforce • Simulation and Debugging Tools: • Mentor Graphics: ModelSim
QuestaSim • Synopsys: VCS
Verdi
DVE • Cadence: NC Verilog
SimVision
Research Interests
HPC
Deepak Kumar Lnu is a Principal Engineer at Synopsys
Inc. with 16+ years of expertise in PCI Express (PCIe) Design and Verification
covering Gen1 through Gen7. He led the development of the industry’s first PCIe Gen7 VIP and pioneered innovations like Polling Compliance Load Board Verification. A named contributor to PCIe 6.0 and 7.0 specifications
his work enables first-silicon success for global semiconductor leaders in AI
and automotive domains. He holds multiple fellowships and is recognized globally for his technical leadership and standardization contributions.
Connect With Me
Experience
Principal Engineer
- Deepak Kumar is a seasoned Principal Engineer with over 16 years of experience in the semiconductor industry, specializing in PCI Express (PCIe) Design and Verification. His expertise spans multiple generations of PCIe (Gen1 through Gen7), where he has contributed to high-speed, low-latency interconnect solutions crucial for Artificial Intelligence (AI), High-Performance Computing (HPC), and advanced computing systems. He is also a recognized contributor to PCI-SIG, with his name proudly included in the PCIe specification. As a key contributor at Synopsys Inc., he has been instrumental in creating and enhancing PCIe Verification IP (VIP), including developing the industry's first-to-market PCIe 6.0 and 7.0 VIP, which empowers customers to validate their designs efficiently and with confidence. His technical acumen is complemented by proficiency in cutting-edge verification methodologies, enabling him to deliver robust, high-quality solutions across a diverse client portfolio. With a customer-focused approach and a commitment to innovation, he thrives on solving complex verification challenges, optimizing workflows, and delivering high-quality results that meet and exceed industry standards. He takes pride in fostering collaboration, mentoring teams, and staying at the forefront of evolving technology trends to continuously deliver impactful solutions.
Education
Delhi Technological University (DTU)
Conferences & Seminars (3)
PCI SIG DevCon 2025
Join us for the upcoming PCI-SIG Developers Conference 2025, which will be held from June 11-12 at the Santa Clara Convention Center in Santa Clara, CA.
Members of the PCI-SIG community including systems architects, designers, engineers and engineering managers, can learn directly from industry PCIe technology experts and participate in technical trainings to gain best practices to improve product interoperability.
PCI SIG DevCon 2023
Members of the PCI-SIG community including systems architects, designers, engineers and engineering managers, can learn directly from industry PCIe technology experts and participate in technical trainings to gain best practices to improve product interoperability.
SemIsrael Verification Day
Back in March 2011, I had the honor of presenting at SemIsrael Verification Day, one of the premier semiconductor events held in Tel Aviv, Israel. Representing nSys Design Systems, I delivered a session titled “Next Generation Verification IPs,” where I spoke about advancements in high-speed interconnect protocol verification and the emerging role of Verification IP (VIP) in accelerating SoC development.
It was an incredible experience to connect with thought leaders and engineers from across the global semiconductor ecosystem. My presentation highlighted the growing challenges in verifying complex IPs and the innovative techniques we were pioneering to improve functional correctness and reduce development cycles—challenges that are even more relevant today.
Awards & Achievements (5)
🏆 Quarterly Excellence Award – a prestigious internal honor presented to top-performing engineers at Synopsys
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🏆 Noble Business Gold Awards for PCIe Gen6 and Gen7 development
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🏆 Titan Business Platinum Award for NextGen Technology
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🏆 Titan Innovation Platinum Award for Innovation in Technology
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🏆 Global Recognition Award 2025
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Professional Memberships (3)
British Computer Society, Swindon
Country: United Kingdom
IEEE - Institute of Electrical and Electronics Engineers
Country: United States
THE INSTITUTION OF ELECTRONICS AND TELECOMMUNICATION ENGINEERS
Country: India
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