About
Deepak Kumar Lnu is a Principal Engineer at Synopsys, Inc. with 16+ years of expertise in PCI Express (PCIe) Design and Verification, covering Gen1 through Gen7. He led the development of the industry’s first PCIe Gen7 VIP and pioneered innovations like Polling Compliance Load Board Verification. A named contributor to PCIe 6.0 and 7.0 specifications, his work enables first-silicon success for global semiconductor leaders in AI, HPC, and automotive domains. He holds multiple fellowships and is recognized globally for his technical leadership and standardization contributions.
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Experience
Principal Engineer
Synopsys, Inc.
Jun-2008 to PresentEducation
Delhi Technological University (DTU)
BE in Electronics and Communication Engineering
Passout Year: 2008Publication
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March, 2025
PCIe polling compliance state verification: Pre-silicon approaches and multi-generation challenges
The Polling Compliance substate in PCI Express link training provides crucial electrical conformity verification but presents significant verification challenges due to its rarely-exercise...
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March, 2025
PCIE VERIFICATION AT HIGH SPEEDS: CHALLENGES, SOLUTIONS, AND FUTURE TRENDS
PCI Express (PCIe) technology is a cornerstone of high-speed data transfer, driving innovation across numerous modern applications. This article delves into the increasingly complex landscap...
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March, 2025
AI-Driven Verification for Compute Express Link (CXL): Challenges, Innovations, and Future
This comprehensive article explores the evolution and challenges of Compute Express Link (CXL) verification methodologies in modern computing environments. The article examines the critical ...
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March, 2025
PCIe L0p low-power state verification: Pre-silicon approaches and challenges
The PCIe 6.0 specification introduces the L0p low-power substrate, enabling dynamic link width scaling to reduce power consumption without interrupting data flow. This feature presents uniqu...
Conference/Seminar/STTP/FDP/Symposium/Workshop
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Mar 2011
SemIsrael Verification Day
SemIsrael - The Israeli Semiconductors Portal ,
Tel Aviv, Israel-
Jun 2023
PCI SIG DevCon 2023
PCI SIG ,
Santa Clara, California, United States-
Jun 2025
PCI SIG DevCon 2025
PCI SIG ,
Santa Clara, California, United StatesMembership

Fellow
THE INSTITUTION OF ELECTRONICS AND TELECOMMUNICATION ENGINEERS
From year 2025 to Presenthttps://www.iete.org/

SIEEE
IEEE - Institute of Electrical and Electronics Engineers
From year 2025 to Presenthttps://www.ieee.org/

Fellow
British Computer Society, Swindon
From year 2025 to PresentHonours & Awards

Global Recognition Award 2025
Global Recognition Award
Year: 2025
Titan Innovation Platinum Award for Innovation in Technology
Titan Innovation
Year: 2025
Titan Business Platinum Award for NextGen Technology
Titan Business
Year: 2025
Noble Business Gold Awards for PCIe Gen6 and Gen7 development
Noble Business
Year: 2025
Quarterly Excellence Award – a prestigious internal honor presented to top-performing engineers at Synopsys
Synopsys
Year: 2024Scholar9 Profile ID
S9-042025-1811312

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