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About

Deepak Kumar Lnu is a Principal Engineer at Synopsys, Inc. with 16+ years of expertise in PCI Express (PCIe) Design and Verification, covering Gen1 through Gen7. He led the development of the industry’s first PCIe Gen7 VIP and pioneered innovations like Polling Compliance Load Board Verification. A named contributor to PCIe 6.0 and 7.0 specifications, his work enables first-silicon success for global semiconductor leaders in AI, HPC, and automotive domains. He holds multiple fellowships and is recognized globally for his technical leadership and standardization contributions.

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Skills

Experience

Organization
Principal Engineer

Synopsys, Inc.

Jun-2008 to Present

Education

Delhi Technological University (DTU)

BE in Electronics and Communication Engineering

Passout Year: 2008

Publication

  • dott image March, 2025

PCIe polling compliance state verification: Pre-silicon approaches and multi-generation challenges

The Polling Compliance substate in PCI Express link training provides crucial electrical conformity verification but presents significant verification challenges due to its rarely-exercise...

  • dott image March, 2025

PCIE VERIFICATION AT HIGH SPEEDS: CHALLENGES, SOLUTIONS, AND FUTURE TRENDS

PCI Express (PCIe) technology is a cornerstone of high-speed data transfer, driving innovation across numerous modern applications. This article delves into the increasingly complex landscap...

  • dott image March, 2025

AI-Driven Verification for Compute Express Link (CXL): Challenges, Innovations, and Future

This comprehensive article explores the evolution and challenges of Compute Express Link (CXL) verification methodologies in modern computing environments. The article examines the critical ...

  • dott image March, 2025

PCIe L0p low-power state verification: Pre-silicon approaches and challenges

The PCIe 6.0 specification introduces the L0p low-power substrate, enabling dynamic link width scaling to reduce power consumption without interrupting data flow. This feature presents uniqu...

Conference/Seminar/STTP/FDP/Symposium/Workshop

Conference
  • dott image Mar 2011

SemIsrael Verification Day

Hosted By:

SemIsrael - The Israeli Semiconductors Portal ,

Tel Aviv, Israel
Back in March 2011, I had the honor of presenting at SemIsrael Verification Day, one of the premier semiconductor events held in Tel Aviv, Israel. Representing nSys Design Systems, I delivered a session titled “Next Generation Verification IPs,” where I spoke about advancements in high-speed interconnect protocol verification and the emerging role of Verification IP (VIP) in accelerating SoC development. It was an incredible experience to connect with thought leaders and engineers from across the global semiconductor ecosystem. My presentation highlighted the growing challenges in verifying complex IPs and the innovative techniques we were pioneering to improve functional correctness and reduce development cycles—challenges that are even more relevant today.
...see more
Conference
  • dott image Jun 2023

PCI SIG DevCon 2023

Hosted By:

PCI SIG ,

Santa Clara, California, United States
Members of the PCI-SIG community including systems architects, designers, engineers and engineering managers, can learn directly from industry PCIe technology experts and participate in technical trainings to gain best practices to improve product interoperability.
...see more
Conference
  • dott image Jun 2025

PCI SIG DevCon 2025

Hosted By:

PCI SIG ,

Santa Clara, California, United States
Join us for the upcoming PCI-SIG Developers Conference 2025, which will be held from June 11-12 at the Santa Clara Convention Center in Santa Clara, CA. Members of the PCI-SIG community including systems architects, designers, engineers and engineering managers, can learn directly from industry PCIe technology experts and participate in technical trainings to gain best practices to improve product interoperability.
...see more

Membership

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Fellow

THE INSTITUTION OF ELECTRONICS AND TELECOMMUNICATION ENGINEERS

From year 2025 to Present

https://www.iete.org/

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SIEEE

IEEE - Institute of Electrical and Electronics Engineers

From year 2025 to Present

https://www.ieee.org/

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Fellow

British Computer Society, Swindon

From year 2025 to Present

Honours & Awards

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Global Recognition Award 2025
Awarded by:

Global Recognition Award

Year: 2025
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Titan Innovation Platinum Award for Innovation in Technology
Awarded by:

Titan Innovation

Year: 2025
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Titan Business Platinum Award for NextGen Technology
Awarded by:

Titan Business

Year: 2025
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Noble Business Gold Awards for PCIe Gen6 and Gen7 development
Awarded by:

Noble Business

Year: 2025
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Quarterly Excellence Award – a prestigious internal honor presented to top-performing engineers at Synopsys
Awarded by:

Synopsys

Year: 2024

Scholar9 Profile ID

S9-042025-1811312

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(4)

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Conferences
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(3)