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Abstract
As microprocessor designs grow increasingly complex, achieving effective coverage closure in Register-Transfer Level (RTL) verification becomes a critical bottleneck. Traditional simulation-based verification techniques often struggle to scale with growing design sizes, leading to delays and increased verification costs. In this paper, we propose a hybrid AI architecture that integrates supervised learning and reinforcement learning models to optimize coverage closure intelligently. The architecture dynamically predicts unverified design areas and suggests directed tests to accelerate verification convergence. We validate our approach on open-source microprocessor designs and report significant improvements in coverage metrics and time-to-closure compared to baseline methods.
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