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Abstract
In the real world of DSP(Digital Signal Processing), the MAC unit ie Multiply-Accumulate Computation holds a pivotal position within the critical processing path. Among its components, the multiplier stands out as a fundamental building block. The altogether performance of the multiply accumulate computation unit is intricately linked to the resources allocated to the multiplier. Hence, this paper proposes low complexity reversible multiplier, specifically engineered to enhance the power efficiency, delay and area of the multiplier. The Multiply-Accumulate Computation(MAC) unit, equipped with a multiplier employing this novel partial product reduction technique, yields significant improvements: a 46% reduction in delay, a 39% decrease in power consumption, and a 17% reduction in area requirements when collate to a MAC unit employing an architecture of a conventional multiplier.
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