Design and Implementation of CMOS Adder Cell with Reduced Leakage Power Technique In 90 nm Technology

CH JANARDHAN "Design and Implementation of CMOS Adder Cell with Reduced Leakage Power Technique In 90 nm Technology". International Journal in Computer and communication Technology, vol: 3, No. 9 Sep. 2014, https://scholar9.com/publication-detail/design-and-implementation-of-cmos-adder-cell-with-16270