Paper Title

Automated Debugging of Hardware Simulation Traces Using Contrastive Learning and Attention Mechanisms

Keywords

hardware debugging
contrastive learning
attention mechanism
simulation traces
fault localization
machine learning for eda

Article Type

Research Article

Journal

Journal of Asian Scientific Research

Publication Info

Volume: 13 | Issue: 3 | Pages: 1-6

Published On

May, 2023

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Abstract

ebugging complex hardware simulation traces is a labor-intensive and error-prone process due to the intricate nature of digital circuit behavior and trace dependencies. In this paper, we propose a novel approach that leverages contrastive learning and attention mechanisms to automate the identification of fault-prone segments in simulation traces. Our methodology embeds trace segments into a learned vector space using a Siamese architecture, while attention layers prioritize signal relevance dynamically. Experimental results on benchmark circuits demonstrate up to 45% improvement in fault localization accuracy compared to traditional pattern-matching approaches. The proposed system paves the way for efficient trace analysis, reducing manual intervention and accelerating verification cycles