Area and Power Optimization of Digital Circuits using CMOS, GDI techniques in 90nm VLSI technology

Abstract

As technology scales to deep sub-micron nodes, the demand for compact, high-performance, and energy-efficient digital systems has intensified, driving interest in alternative logic design techniques beyond conventional CMOS. Gate Diffusion Input (GDI) emerges as a promising methodology, enabling the realization of complex logic functions with significantly fewer transistors, resulting in substantial reductions in silicon area, power consumption, and interconnect complexity. In this paper, a comparative analysis of digital circuits—including basic logic gates, multiplexers, and adders—implemented using both CMOS and GDI techniques were presented, targeting the 90nm technology node. The designs were implemented and simulated using the Cadence Virtuoso tool suite, with schematic entry, transient, DC, and AC analyses performed to ensure accurate modelling. Simulation results revealed that GDI-based circuits achieve up to 45% area reduction and notable improvements in power efficiency compared to their CMOS counterparts, with minimal degradation in speed. The reduced transistor count and power consumption in GDI circuits enhance energy efficiency, making them well-suited for low-power and area-constrained applications such as wearable devices, biomedical systems. Implementation of these circuits with CMOS and GDI techniques using Cadence Virtuoso confirms the practical integration of GDI in advanced nanometer-scale digital circuit design.