Design of 4-bit ALU for low-power and High-speed Applications.

Abstract

This paper presents a novel design and optimization of a 4-bit Arithmetic Logic Unit (ALU) utilizing 90nm CMOS technology, specifically addressing the longstanding carry-out issue prevalent in existing architectures. Notably, our proposed 4-bit ALU architecture successfully minimizes delay and power consumption by incorporating an optimized carry-out design employing AND gates. A comprehensive comparison of three logic styles - Pass Transistor Logic (PTL), Complementary Metal-Oxide-Semiconductor (CMOS), and Transmission Gate Logic (TGL) - is conducted, yielding significant improvements in power-delay tradeoffs. Simulation results validate the efficacy of our design in resolving the carry-out issue, making it an attractive solution for low-power, high-speed digital applications.