UVM-BASED POWER-AWARE VERIFICATION CLOSURE USING DYNAMIC VOLTAGE AND FREQUENCY SCALING (DVFS) MODELS

Abstract

Power-aware verification has become a cornerstone in the functional validation of modern System-on-Chip (SoC) designs, especially those targeting low-power domains such as mobile and wearable devices. This paper presents a Universal Verification Methodology (UVM)-based approach for achieving verification closure using Dynamic Voltage and Frequency Scaling (DVFS) models integrated with Unified Power Format (UPF). The proposed verification framework dynamically simulates power mode transitions in real time, enabling accurate capture of corner-case failures and illegal state transitions across voltage/frequency domains. We demonstrate how DVFS-aware testbench infrastructure interacts with power controllers and simulates multi-voltage scenarios to validate correctness, functional safety, and energy efficiency. Our methodology improves regression throughput and robustness in low-power verification by bridging design and power-intent coverage gaps. The proposed approach is validated through case studies on low-power SoCs representative of commercial mobile and wearable platforms.