FULL PDF
Abstract
Finite Impulse Response (FIR) filters are widely used in digital signal processing (DSP) applications due to their stability and linear-phase characteristics. However, their high computational complexity, primarily due to extensive multiplication and addition operations, can limit their speed and efficiency. In this paper we present a high-speed FIR filter design by integrating segmented arithmetic (SA) based compressors and approximate adders to enhance computation speed. The proposed approach replaces conventional adder trees with segmented arithmetic (SA) based compressor circuits (such as 4:2 and 7:3 compressors), which efficiently reduce partial products during multiplication. Additionally, optimized approximate adders, are employed to further minimize latency and hardware complexity. In this we mainly focus on the design of 3-tap FIR filter and the proposed architecture is implemented on FPGA, which is of Target device- XC3S50-5pq208 belonging to the Spartan 6 family using Xilinx 14-7 ISE software. The Simulation results are obtained and analyzed that the proposed architecture achieves lower power consumption 2.3mv with critical path delay 17.450ns, and area utilization 28,500µ m^2.
View more >>