Scalable Machine Learning Pipelines for Formal Verification Support in High-Level Synthesis Flows

Abstract

The growing complexity of hardware design calls for integrating machine learning (ML) pipelines into high-level synthesis (HLS) flows to assist formal verification (FV) processes. This research explores scalable ML-driven pipelines that predict potential verification bottlenecks early during HLS, aiming to optimize verification resources and speed up convergence. We propose a compact, scalable framework evaluated across diverse designs, highlighting the predictive accuracy and resource scalability. Our findings demonstrate that incorporating ML not only reduces verification time but also enhances the correctness assurance of synthesized hardware, establishing a crucial link between HLS automation and formal methods.