Optimization of Coplanar Full Adder Design Using Five-Input Majority Logic in Quantum-Dot Cellular Automata

Abstract

Quantum-Dot Cellular Automata (QCA) technology represents a significant advancement in nano-scale computing, offering advantages over traditional CMOS-based circuits in terms of speed, power efficiency, and miniaturization. This paper presents an optimized design for a coplanar full adder utilizing five-input majority logic gates within the QCA framework. The proposed design addresses the limitations of conventional QCA full adders by reducing cell count, area, and interconnect complexity while improving performance metrics such as speed and power consumption. By leveraging the unique properties of five-input majority gates, the design integrates multiple logical functions into a single gate, leading to a more compact and efficient circuit. Comprehensive simulations using QCADesigner demonstrate that the optimized full adder outperforms existing designs in terms of reduced delay, lower power consumption, and minimized area. The results indicate improvements of approximately 20-30% in cell count and area, a 15-25% reduction in delay, and a 10-20% decrease in power consumption compared to traditional QCA full adder designs. These enhancements make the proposed design highly suitable for high-performance, low-power applications. Future work will focus on scaling the design for larger circuits, incorporating fault tolerance, and exploring fabrication techniques to bridge theoretical designs with practical implementations. This study highlights the potential of QCA technology to advance digital circuit design and offers a foundation for future innovations in nano-scale computing.