low power and area efficient 64 bit floating point vedic multiplier design for high speed operation in DSP applications using 90nm technology

Srinivasarao Udara "low power and area efficient 64 bit floating point vedic multiplier design for high speed operation in DSP applications using 90nm technology". , https://scholar9.com/publication-detail/low-power-and-area-efficient-64-bit-floating-point-18824