HYBRID VERIFICATION METHODOLOGIES COMBINING SIMULATION AND EMULATION FOR HIGH COMPLEXITY SYSTEM-ON-CHIP DESIGNS

Abstract

The verification of System-on-Chip (SoC) designs has become increasingly challenging due to growing complexity, integration density, and performance requirements. Traditional simulation techniques, although highly accurate, are insufficient alone to manage verification cost and turnaround time. Conversely, hardware emulation offers speed but lacks detailed visibility. This paper explores hybrid verification methodologies that combine simulation and emulation to achieve comprehensive, scalable, and efficient SoC verification. Key methodologies, recent advancements, and potential optimizations are discussed