HARDWARE TROJAN DETECTABILITY ENHANCEMENT USING LOGIC LOCKING AND POWER DISCREPANCY ANALYSIS

Abstract

Most semiconductor companies outsource the manufacturing of their chip designs to third-party fabrication foundries. However, untrusted foundries pose significant security risks, including intellectual property (IP) piracy and the insertion of hardware Trojans (HTs)—malicious modifications intended to sabotage circuits. These HTs can lead to increased power consumption, but due to process variations and the minimal footprint of small HTs in large-scale circuits, traditional power consumption analysis (PCA) often fails to detect them. To address this challenge, circuits can be partitioned into smaller sub-circuits, with PCA applied individually to each. In this paper, we propose a novel logic locking [2] technique designed to enhance the effectiveness of PCA-based HT detection. Building on the "RESTORATION" approach introduced in [1], our method increases the power contribution of HTs relative to the overall circuit power, thereby improving their detectability. Experimental results at both the gate level and post-synthesis demonstrate that the proposed locking scheme facilitates more efficient and reliable HT detection compared to existing logic locking [2] techniques.