MD ASIF
"Design and FPGA Implementation of Optimized 32-Bit Vedic Multiplier and Square Architectures".
International Journal of Emerging Research in Management and Technology,
vol: 6,
No. 5
May. 2017,
pp: ,
https://scholar9.com/publication-detail/design-and-fpga-implementation-of-optimized-32bit-4323
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