Area efficient High Level Logic Synthesis Using 5-Input Majority Gate Based on Multiplexer.

D. AJITHA "Area efficient High Level Logic Synthesis Using 5-Input Majority Gate Based on Multiplexer.". Proceedings of National Conference on Recent Advancements in Nanoelectronics, Jan. 1970, https://scholar9.com/publication-detail/area-efficient-high-level-logic-synthesis-using-5-21459