KARTHIKEYAN A
"An Efficient VLSI Implementation for 64 Bit Error Tolerant Adders".
International Journal of Advance Research in Science and Engineering,
vol: 4,
No. 2
Feb. 2015, pp: 596-603,
https://scholar9.com/publication-detail/an-efficient-vlsi-implementation-for-64-bit-error-6641
