Yogini Yogini,
"4-Bit Fast Adder Design: Topology and Layout with Self-Resetting Logic for low Power VLSI circuits". , vol:
7, No.2
Jan. 1970, pp: 197 205, https://scholar9.com/publication-detail/4bit-fast-adder-design-topology-and-layout-with-22903
Copy Text
True scholar network
