About
To secure a challenging position in VLSI domain from a reputable organization to expand my learnings , knowledge and skil ls.
Skills & Expertise
Verilog
VHDL
SystemVerilog
Universal Verification Methodology (UVM)
UART
I2C
SPI
C Programming
Linux
Windows
iOS
RF Circuit Designing
PCB Designing
Xilinx ISE
Icarus Verilog
Mentor Graphics Questasim
Mentor Graphics Modelsim
Yosys
OrCAD Capture CIS
Allegro
SystemVue
Pspice
Research Interests
Communication
Teamwork
Problem Solving
Analytical
Time Management
Connect With Me
Experience
Project Engineer (Contract.)
Education
JBIET
NARAYANA JUNIOR COLLEGES.
Sri Chaitanya Techno School
Projects
On Board Computer
-The main focus of this project was to study the architecture of On Board Computer, i.e . concerning over all the possible parameters of an on board computer which must be sustainable in extreme atmospheric conditions and over different terrains.
Design of Coherent RF Up & Down Converter
-The aim of this project is to design a circuit (applicable for C to Ku Band) which could Down convert the received RF signal and Up convert the same signal with less power consumption and transmit back to the target which blocks it to access the confidential devices.
Design of 8 bit encoder & decoder architecture based FP GA imple mentation of POLAR CODES for 5G applications
at VedIC school of VLSI Design . -Linear Block error correcting codes are an emblematic in the upcoming 5G broadband communication, in which polar codes are one amo ng those codes consisting of an efficient channel polarization technique achieving higher throughput and lesser latency.
Verification of Bus Architecture ba sed Encryption Standard
The aim of this work is to verify three different working architectural designs for AES cipher, which is a symmetric block encrypt ion standard. This also includes an AMBA AHB interface, which is an open standard that defines interconnection of blocks in SOC.
Certificates & Licenses (6)
Modelling the Etching of Nano Structures
conducted by IEEE.
Quantum Computing
conducted by IEEE Quantum Special Interest Group (SIG) at IIIT Hyderabad , supported by Microsoft India Pvt. Ltd .
Electronic & Photonic Packaging
conducted by IEEE (CAS/ EDS ) & IEEE Photonics Society at AMS Semiconductors India Pvt. Ltd . in association with Telangana Govt. Initiatives in Photonics.
PCB Design using Cadence OrCAD Capture, PSpice and Allegro
Complet ed 8.5 hours of PCB Design using Cadence OrCAD Capture, PSpice and Allegro online course in Udemy
VLSI System Design Using Open Source EDA
have been awarded with Grade A(84.44%) , organized by E & ICT Academy, IIT Guwahati held from 23rd Sept 2019 to 27th Sept 2019 , supported by Ministry of Electronics & Information Technology (Meit Y), Govt. Of India in association with VLSI System Design (VSD) Corp. Pvt. Ltd.
VLSI Front -end RTL Design & Verification
Professional Memberships (2)
INTERNATIONAL ASSOCIATION of ENGINEERS ( IAENG )
INSTITUTE of ELECTRICAL & ELECTRONICS ENGINEERING ( IEEE)
Publications (2)
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