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About

I am currently pursuing a Ph.D., building on a strong foundation in electronics and computer engineering, particularly in the VLSI domain. My research interests extend to Artificial Intelligence and Machine Learning, where I explore innovative solutions utilizing Docker and cloud VMs. In addition to my research, I am proficient in multiple programming languages, including C, C++, and Java, with a particular focus on object-oriented programming and algorithm analysis. My academic journey is complemented by expertise in data structures, finite automata, and various algorithmic techniques, including heap trees and graph algorithms. This diverse technical background allows me to approach problems from a multidisciplinary perspective, integrat ing advanced technical knowledge with cutting-edge research methodologies.

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Skills

Experience

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SKR ENGINEERING COLLEGE

Jan-2014 to Nov-2018
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MASTERMINDS INISTUITE OF TECHNOLOGY

Dec-2018 to Jul-2021
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SRI VENKATESWARA INISTITUTE OF TECHNOLOGY

Aug-2021 to Aug-2024

Education

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Audisanakra college of engineering

Master of Technology (M.Tech) in VLSI

Passout Year: 2014
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Narayana college of engineering

B.Tech in Electronics and Communication

Passout Year: 2010
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AL-HUDA POLYTECHNIC COLLEGE

Diploma in Electronics and Communication

Passout Year: 2007

Publication

Role in Research Journals

Projects

Jan-1970 to Jan-1970

Implimentation of A 16-bit RISC Processor for Convolution Application

RISC architecture is used across a wide range of platforms from Cellular phones to super computers.In this paper,a 16- bit RISC processor is designed, which utilizes minimum functional units without compromising in performance. The design is based on architectural modification made in the incremented circuit which is used in program counter. A Low Power Area Efficient carry select adder and a high speed low power modified Wallace tree multiplier has been designed to improving performance of ALU in RISC processor. The RISC processor has been realized using Verilog HDL
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Conference/Seminar/STTP/FDP/Symposium/Workshop

FDP
  • dott image Jun 2023

National Level One Week Faculty Development Programme on “Recent Trends in Data Science for Engineering”

Hosted By:

Chaitanya Bharathi Institute of Technology, Proddatur (CBIT Proddatur) ,

Anantapur, Andhra Pradesh, India
FDP
  • dott image Feb 2024

RIKSHIT BHARATH-2047 ROLE OF ENGINEERING FACULTY

Hosted By:

SVIT COLLEGE OF ENGINEERING ,

Anantapur, Andhra Pradesh, India
Workshop
  • dott image Sep 2015

Hands on Experience of Microwave Devices

Hosted By:

GKCE, Sullurpet. ,

Anantapur, Andhra Pradesh, India
Workshop
  • dott image Jun 2016

CADENCE PRACTICE

Hosted By:

ASCET COLEEGE ,

Anantapur, Andhra Pradesh, India

Certificates

Membership

Invited Position

Honours & Awards

Doctoral and Master Thesis Guided

Patent

Scholar9 Profile ID

S9-092024-0205951

Publication
Publication

(0)

Citations
Citations

(0)

Network
Network

(0)

Conferences
Conferences/Seminar

(4)

Academic Identity

ORCID
ORCID
Scopus Profile
Scopus Profile
https://id.elsevier.com/settings/redirect?code=5k5Ra0IQyz-xmDIIQwhCw25Bn8cmaBVzOZk5Ump7
Web of Science Researcher ID
Web of Science Scholar ID
LEM-5489-2024
Google Scholar Profile
Google Scholar Profile
https://scholar.google.com/citations?user=Uj9gPfkAAAAJ&hl=en

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