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Journal Photo for Design Automation for Embedded Systems
Peer reviewed only Open Access

Design Automation for Embedded Systems (DAES)

Publisher : Springer Nature
Hardware and Architecture Software Hardware-Software Co-design
e-ISSN 1572-8080
p-ISSN 0929-5585
Issue Frequency Quarterly
Impact Factor 0.9
Est. Year 1996
Mobile 4962214870
Language English
APC YES
Email customerservice@springernature.com

Journal Descriptions

Design Automation for Embedded Systems is a multidisciplinary journal dedicated to cutting-edge research in the automation of embedded systems design. As embedded systems evolve to meet the demands of increasingly complex and intelligent applications—spanning sectors from automotive and aerospace to IoT and edge AI—the need for advanced design methodologies and tools has never been greater. The journal focuses on innovations that push the boundaries of how embedded systems are architected, designed, verified, and deployed. Core areas of interest include: Hardware-Software Co-design, synthesis, and optimization for embedded systems, FPGAs, multicore, and heterogeneous systems AI-assisted design and optimization workflows, including agentic systems and reinforcement-learning-based automation System-level methodologies leveraging large language models (LLMs) for specification, code synthesis, hardware/software partitioning, and design-space exploration LLM-aided tools for Register-Transfer Level (RTL) design, High-Level Synthesis (HLS), and formal verification

Design Automation for Embedded Systems (DAES) is :-

  • International, Peer-Reviewed, Open Access, Refereed, Hardware and Architecture, Software, Hardware-Software Co-design, synthesis, and optimization for embedded systems, FPGAs, multicore, heterogeneous systems, AI-assisted design and optimization workflows, including agentic systems and reinforcement-learning-based automation, System-level methodologies leveraging large language models (LLMs) for specification, code synthesis, hardware/software partitioning, design-space exploration, LLM-aided tools for Register-Transfer Level (RTL) design, High-Level Synthesis (HLS), formal verification, AI hardware acceleration and co-design methodologies for deploying machine learning workloads on edge and embedded platforms , Online or Print , Quarterly Journal

  • UGC Approved, ISSN Approved: P-ISSN P-ISSN: 0929-5585, E-ISSN: 1572-8080, Established: 1996, Impact Factor: 0.9
  • Does Not Provide Crossref DOI
  • Not indexed in Scopus, WoS, DOAJ, PubMed, UGC CARE

Indexing